Data can be sent in many different forms in a computer system or between computer systems (e.g., over a network). In some systems, data is grouped together and sent as a packet. PCI Express (Peripheral Component Interconnect Special Interest Group's Peripheral Component Interconnect Express 1.0 specification, published Jul. 22, 2002) is one example of a protocol for packetizing and transmitting data. Regardless of the protocol being used, the transmission of packets requires some level of overhead and minimum packet size.
For example, some packets require a header (e.g., overhead) that contains information regarding the contents and/or destination of the packet. If a minimum packet size is required before sending the packet, some systems will “stuff” additional bits into a packet that does not meet the minimum size requirement. The stuffed bits contain no useful information and reduce the efficiency of the system.
Following are some examples of PCI Express transactions that typically require bit stuffing to meet minimum packet size requirements. First, a simple sequence to an IO-mapped (e.g., input/output mapped) device requires an 8-bit IO write transaction to an index register followed by an 8-bit IO cycle to the corresponding data register. This translates into two full PCI Express transactions, both of minimum length and efficiency.
Second, reading a FIFO (e.g., first-in, first-out) or doorbell register consists of reading the same address repeatedly with a separate PCI Express transaction each time. Third, some special memory transactions (e.g., programming a flash memory device) require byte or word writes in command sequence order. Each of these writes requires a separate PCI Express transaction.
Thus, each of these three processes require multiple PCI Express transactions of minimum length, which is likely to involve the inefficient transmission of useless bits due to bit stuffing. Moreover, each additional PCI Express transaction requires system resources in order to form packets, to transmit packets, and to acknowledge packet transmission.
The drawbacks of packet overhead and minimum packet size are particularly noticeable in situations where data traffic is primarily routed to low bandwidth peripheral devices and IO devices since utilization of these devices can be low. Low utilization translates into wasted power, particularly in low power systems. For switches, low utilization can result in inefficient performance and arbitration inefficiencies.